I. Field of the Disclosure
The technology of the disclosure relates generally to magnetic random access memory (MRAM) bit cells and, more particularly, to the interconnection between a magnetic tunnel junction (MTJ) and an access transistor of the MRAM bit cells.
II. Background
Semiconductor storage devices are used in integrated circuits (ICs) in electronic devices to provide data storage. One example of a semiconductor storage device is magnetic random access memory (MRAM). MRAM is non-volatile memory in which data is stored by programming a magnetic tunnel junction (MTJ) as part of an MRAM bit cell. One advantage of an MRAM is that MTJs can retain stored information even when power is turned off. This is because data is stored in the MTJ as a small magnetic element rather than as an electric charge or current.
FIG. 1 is a schematic diagram of an MRAM bit cell 100 including an MTJ 102 to store non-volatile data that can be provided in an MRAM array in an IC. A metal oxide semiconductor (MOS) (typically n-type MOS, i.e., NMOS) access transistor 104 (“access transistor 104”) is provided to control reading and writing to the MTJ 102. A drain node (D) of the access transistor 104 is coupled to a bottom electrode 106 of the MTJ 102, which is coupled to a pinned layer 108 of the MTJ 102. A word line (WL) is coupled to a gate node (G) of the access transistor 104. A source node (S) of the access transistor 104 is coupled to a voltage source (VS) through a source line (SL). The voltage source (VS) provides a voltage (VSL) on the source line (SL). A bit line (BL) is coupled to a top electrode 110 of the MTJ 102, which is coupled to a free layer 112 of the MTJ 102. The pinned layer 108 and the free layer 112 are separated by a tunnel barrier layer 114. The magnetic orientation of the free layer 112 can be changed, but the magnetic orientation of the pinned layer 108 remains fixed or “pinned.” Accordingly, data can be stored in the MTJ 102 based on the magnetic orientation of the free layer 112. When the magnetic orientations of the pinned and free layers 108, 112 are anti-parallel (AP) to each other, a first memory state exists (e.g., a logical ‘1’). When the magnetic orientations of the pinned and free layers 108, 112 are parallel (P) to each other, a second memory state exists (e.g., a logical ‘0’).
When writing data to the MTJ 102 in FIG. 1, the gate node (G) of the access transistor 104 is activated by activating the word line (WL). A voltage differential between a voltage (VBL) on the bit line (BL) and the voltage (VSL) on the source line (SL) is applied. As a result, a write current (I) is generated between the drain node (D) and the source node (S) of the access transistor 104. If the magnetic orientation of the MTJ 102 in FIG. 1 is to be changed from AP to P, a write current (IAP-P) flowing from the top electrode 110 to the bottom electrode 106 is generated to change the magnetic orientation of the free layer 112 to P with respect to the pinned layer 108. If the magnetic orientation is to be changed from P to AP, a write current (IP-AP) flowing from the bottom electrode 106 to the top electrode 110 is generated to change the magnetic orientation of the free layer 112 to AP with respect to the pinned layer 108. The magnetic orientations of the pinned and free layers 108, 112 can be sensed to read data stored in the MTJ 102 by sensing a resistance when the write current (I) flows through the MTJ 102.
Advances in fabrication processes allow nodes to be scaled down to reduce chip area and/or increase the number of semiconductor devices in an IC. However, fabrication process limitations may limit scaling down interconnections (lines or islands) in an IC. For example, in an IC including the MRAM bit cell 100, the access transistor 104 is conventionally disposed in an active area at or near a substrate of the IC. The MTJ 102 is conventionally disposed at a high interconnection layer (e.g., metal layer) of the IC to facilitate an external connection in the IC for the bit line (BL). Thus, the bottom electrode 106 is interconnected to the drain node (D) of the access transistor 104 by a drain column that includes a plurality of intermediate interconnections (lines or islands), of corresponding interconnection layers. These interconnections (lines or islands) are conventionally formed by a lithography process on corresponding interconnection layers. However, due to limitations in lithography processes, each interconnection line and/or island requires a minimum area, and separation from adjacent interconnections (lines or islands) by a minimum distance. Accordingly, a resulting interconnection line pitch (i.e., the distance from a center of an interconnection (line or island) to a center of an adjacent interconnection (line or island)) limits the number of interconnections (lines or islands) that can be formed in an IC, and therefore limits the number of interconnection paths to interconnect semiconductor devices therein. Thus, although advanced fabrication processes may reduce the size of semiconductor elements in an IC, such as transistors, limitations associated with forming interconnections (lines or islands) to interconnect semiconductor elements and devices can limit the number of semiconductor devices that can be interconnected in the IC and, therefore, also limit further scaling down devices, such as the MRAM bit cell 100 in FIG. 1.